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   <div id="projectname">DM-CtrlH7-BF-DevProgram<span id="projectnumber">&#160;beta 0.1</span>
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   <div id="projectbrief">C.ONE Studio Damiao Development Board Framework</div>
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  <div class="headertitle"><div class="title">Cache Functions <div class="ingroups"><a class="el" href="group___c_m_s_i_s__core__register.html">Defines and Type Definitions</a> &raquo; <a class="el" href="group___c_m_s_i_s___c_o_r_e.html">Status and Control Registers</a> &raquo; <a class="el" href="group___c_m_s_i_s___n_v_i_c.html">Nested Vectored Interrupt Controller (NVIC)</a> &raquo; <a class="el" href="group___c_m_s_i_s___s_c_b.html">System Control Block (SCB)</a> &raquo; <a class="el" href="group___c_m_s_i_s___s_cn_s_c_b.html">System Controls not in SCB (SCnSCB)</a> &raquo; <a class="el" href="group___c_m_s_i_s___sys_tick.html">System Tick Timer (SysTick)</a> &raquo; <a class="el" href="group___c_m_s_i_s___i_t_m.html">Instrumentation Trace Macrocell (ITM)</a> &raquo; <a class="el" href="group___c_m_s_i_s___d_w_t.html">Data Watchpoint and Trace (DWT)</a> &raquo; <a class="el" href="group___c_m_s_i_s___t_p_i.html">Trace Port Interface (TPI)</a> &raquo; <a class="el" href="group___c_m_s_i_s___m_p_u.html">Memory Protection Unit (MPU)</a> &raquo; <a class="el" href="group___c_m_s_i_s___f_p_u.html">Floating Point Unit (FPU)</a> &raquo; <a class="el" href="group___c_m_s_i_s___core_debug.html">Core Debug Registers (CoreDebug)</a> &raquo; <a class="el" href="group___c_m_s_i_s__core__bitfield.html">Core register bit field macros</a> &raquo; <a class="el" href="group___c_m_s_i_s__core__base.html">Core Definitions</a> &#124; <a class="el" href="group___c_m_s_i_s__core__register.html">Defines and Type Definitions</a> &raquo; <a class="el" href="group___c_m_s_i_s___c_o_r_e.html">Status and Control Registers</a> &raquo; <a class="el" href="group___c_m_s_i_s___n_v_i_c.html">Nested Vectored Interrupt Controller (NVIC)</a> &raquo; <a class="el" href="group___c_m_s_i_s___s_c_b.html">System Control Block (SCB)</a> &raquo; <a class="el" href="group___c_m_s_i_s___s_cn_s_c_b.html">System Controls not in SCB (SCnSCB)</a> &raquo; <a class="el" href="group___c_m_s_i_s___sys_tick.html">System Tick Timer (SysTick)</a> &raquo; <a class="el" href="group___c_m_s_i_s___i_t_m.html">Instrumentation Trace Macrocell (ITM)</a> &raquo; <a class="el" href="group___c_m_s_i_s___d_w_t.html">Data Watchpoint and Trace (DWT)</a> &raquo; <a class="el" href="group___c_m_s_i_s___t_p_i.html">Trace Port Interface (TPI)</a> &raquo; <a class="el" href="group___c_m_s_i_s___m_p_u.html">Memory Protection Unit (MPU)</a> &raquo; <a class="el" href="group___c_m_s_i_s___f_p_u.html">Floating Point Unit (FPU)</a> &raquo; <a class="el" href="group___c_m_s_i_s___core_debug.html">Core Debug Registers (CoreDebug)</a> &raquo; <a class="el" href="group___c_m_s_i_s__core__bitfield.html">Core register bit field macros</a> &raquo; <a class="el" href="group___c_m_s_i_s__core__base.html">Core Definitions</a> &raquo; <a class="el" href="group___c_m_s_i_s___core___function_interface.html">Functions and Instructions Reference</a> &raquo; <a class="el" href="group___c_m_s_i_s___core___n_v_i_c_functions.html">NVIC Functions</a> &raquo; <a class="el" href="group___c_m_s_i_s___core___fpu_functions.html">FPU Functions</a></div></div></div>
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<p>Functions that configure Instruction and Data cache.  
<a href="#details">More...</a></p>
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<tr class="heading"><td colspan="2"><h2 id="header-groups" class="groupheader"><a id="groups" name="groups"></a>
Topics</h2></td></tr>
<tr class="memitem:CMSIS_5FCore_5FSysTickFunctions" id="r_CMSIS_5FCore_5FSysTickFunctions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_m_s_i_s___core___sys_tick_functions.html">SysTick Functions</a></td></tr>
<tr class="memdesc:group___c_m_s_i_s___core___sys_tick_functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions that configure the System. <br /></td></tr>
<tr class="memitem:ga980ffe52af778f2535ccc52f25f9a7de" id="r_ga980ffe52af778f2535ccc52f25f9a7de"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga980ffe52af778f2535ccc52f25f9a7de">SCB_EnableICache</a> (void)</td></tr>
<tr class="memdesc:ga980ffe52af778f2535ccc52f25f9a7de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable I-Cache.  <br /></td></tr>
<tr class="memitem:ga56baa06298799dea5f207d4c12d9d4a6" id="r_ga56baa06298799dea5f207d4c12d9d4a6"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga56baa06298799dea5f207d4c12d9d4a6">SCB_DisableICache</a> (void)</td></tr>
<tr class="memdesc:ga56baa06298799dea5f207d4c12d9d4a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable I-Cache.  <br /></td></tr>
<tr class="memitem:ga62419cb7e6773e3d9236f14e458c1b05" id="r_ga62419cb7e6773e3d9236f14e458c1b05"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga62419cb7e6773e3d9236f14e458c1b05">SCB_InvalidateICache</a> (void)</td></tr>
<tr class="memdesc:ga62419cb7e6773e3d9236f14e458c1b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invalidate I-Cache.  <br /></td></tr>
<tr class="memitem:gaf6bed290ff6916337b0ce6c09131f699" id="r_gaf6bed290ff6916337b0ce6c09131f699"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf6bed290ff6916337b0ce6c09131f699">SCB_InvalidateICache_by_Addr</a> (void *addr, int32_t isize)</td></tr>
<tr class="memdesc:gaf6bed290ff6916337b0ce6c09131f699"><td class="mdescLeft">&#160;</td><td class="mdescRight">I-Cache Invalidate by address.  <br /></td></tr>
<tr class="memitem:ga3861db932100ccb53f994e2cc68ed79c" id="r_ga3861db932100ccb53f994e2cc68ed79c"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3861db932100ccb53f994e2cc68ed79c">SCB_EnableDCache</a> (void)</td></tr>
<tr class="memdesc:ga3861db932100ccb53f994e2cc68ed79c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable D-Cache.  <br /></td></tr>
<tr class="memitem:gafe64b44d1a61483a947e44a77a9d3287" id="r_gafe64b44d1a61483a947e44a77a9d3287"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gafe64b44d1a61483a947e44a77a9d3287">SCB_DisableDCache</a> (void)</td></tr>
<tr class="memdesc:gafe64b44d1a61483a947e44a77a9d3287"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable D-Cache.  <br /></td></tr>
<tr class="memitem:ga99fe43c224644881935de135ceaa2dd9" id="r_ga99fe43c224644881935de135ceaa2dd9"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga99fe43c224644881935de135ceaa2dd9">SCB_InvalidateDCache</a> (void)</td></tr>
<tr class="memdesc:ga99fe43c224644881935de135ceaa2dd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invalidate D-Cache.  <br /></td></tr>
<tr class="memitem:gaf5585be5547cc60585d702a6129f4c17" id="r_gaf5585be5547cc60585d702a6129f4c17"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf5585be5547cc60585d702a6129f4c17">SCB_CleanDCache</a> (void)</td></tr>
<tr class="memdesc:gaf5585be5547cc60585d702a6129f4c17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clean D-Cache.  <br /></td></tr>
<tr class="memitem:ga5b22ca58709fadc326da83197a2f28bb" id="r_ga5b22ca58709fadc326da83197a2f28bb"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga5b22ca58709fadc326da83197a2f28bb">SCB_CleanInvalidateDCache</a> (void)</td></tr>
<tr class="memdesc:ga5b22ca58709fadc326da83197a2f28bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clean &amp; Invalidate D-Cache.  <br /></td></tr>
<tr class="memitem:ga9945b206324ddbcd32818f1a4e49df83" id="r_ga9945b206324ddbcd32818f1a4e49df83"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9945b206324ddbcd32818f1a4e49df83">SCB_InvalidateDCache_by_Addr</a> (void *addr, int32_t dsize)</td></tr>
<tr class="memdesc:ga9945b206324ddbcd32818f1a4e49df83"><td class="mdescLeft">&#160;</td><td class="mdescRight">D-Cache Invalidate by address.  <br /></td></tr>
<tr class="memitem:gab86b0b49bac2b14b21cc1590009efac5" id="r_gab86b0b49bac2b14b21cc1590009efac5"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab86b0b49bac2b14b21cc1590009efac5">SCB_CleanDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
<tr class="memdesc:gab86b0b49bac2b14b21cc1590009efac5"><td class="mdescLeft">&#160;</td><td class="mdescRight">D-Cache Clean by address.  <br /></td></tr>
<tr class="memitem:ga853737b61ec075250d5991748fdd0e83" id="r_ga853737b61ec075250d5991748fdd0e83"><td class="memItemLeft" align="right" valign="top">__STATIC_FORCEINLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga853737b61ec075250d5991748fdd0e83">SCB_CleanInvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
<tr class="memdesc:ga853737b61ec075250d5991748fdd0e83"><td class="mdescLeft">&#160;</td><td class="mdescRight">D-Cache Clean and Invalidate by address.  <br /></td></tr>
<tr class="memitem:ga3d672529cd193537fe2a0141931c6ad9" id="r_ga3d672529cd193537fe2a0141931c6ad9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga3d672529cd193537fe2a0141931c6ad9">CCSIDR_WAYS</a>(x)</td></tr>
<tr class="memitem:gaf20feee7c52fee32b48ee0d2ceaaf932" id="r_gaf20feee7c52fee32b48ee0d2ceaaf932"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaf20feee7c52fee32b48ee0d2ceaaf932">CCSIDR_SETS</a>(x)</td></tr>
<tr class="memitem:ga8f36551f2593cd3715d1e68e37f97f12" id="r_ga8f36551f2593cd3715d1e68e37f97f12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga8f36551f2593cd3715d1e68e37f97f12">__SCB_DCACHE_LINE_SIZE</a>&#160;&#160;&#160;32U</td></tr>
<tr class="memitem:gadd99421e7a7d7121063ef94b49f97e90" id="r_gadd99421e7a7d7121063ef94b49f97e90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gadd99421e7a7d7121063ef94b49f97e90">__SCB_ICACHE_LINE_SIZE</a>&#160;&#160;&#160;32U</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<p>Functions that configure Instruction and Data cache. </p>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="ga8f36551f2593cd3715d1e68e37f97f12" name="ga8f36551f2593cd3715d1e68e37f97f12"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8f36551f2593cd3715d1e68e37f97f12">&#9670;&#160;</a></span>__SCB_DCACHE_LINE_SIZE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __SCB_DCACHE_LINE_SIZE&#160;&#160;&#160;32U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR </p>

</div>
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<a id="gadd99421e7a7d7121063ef94b49f97e90" name="gadd99421e7a7d7121063ef94b49f97e90"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gadd99421e7a7d7121063ef94b49f97e90">&#9670;&#160;</a></span>__SCB_ICACHE_LINE_SIZE</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define __SCB_ICACHE_LINE_SIZE&#160;&#160;&#160;32U</td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR </p>

</div>
</div>
<a id="gaf20feee7c52fee32b48ee0d2ceaaf932" name="gaf20feee7c52fee32b48ee0d2ceaaf932"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf20feee7c52fee32b48ee0d2ceaaf932">&#9670;&#160;</a></span>CCSIDR_SETS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CCSIDR_SETS</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>x</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(((x) &amp; <a class="code hl_define" href="group___c_m_s_i_s___c_o_r_e.html#ga47d1f01185d7a039334031008386c5a8">SCB_CCSIDR_NUMSETS_Msk</a>      ) &gt;&gt; <a class="code hl_define" href="group___c_m_s_i_s___c_o_r_e.html#ga1028d2c238f74d2aa021f53ffbe8d7ab">SCB_CCSIDR_NUMSETS_Pos</a>      )</div>
<div class="ttc" id="agroup___c_m_s_i_s___c_o_r_e_html_ga1028d2c238f74d2aa021f53ffbe8d7ab"><div class="ttname"><a href="group___c_m_s_i_s___c_o_r_e.html#ga1028d2c238f74d2aa021f53ffbe8d7ab">SCB_CCSIDR_NUMSETS_Pos</a></div><div class="ttdeci">#define SCB_CCSIDR_NUMSETS_Pos</div><div class="ttdef"><b>Definition</b> core_armv81mml.h:884</div></div>
<div class="ttc" id="agroup___c_m_s_i_s___c_o_r_e_html_ga47d1f01185d7a039334031008386c5a8"><div class="ttname"><a href="group___c_m_s_i_s___c_o_r_e.html#ga47d1f01185d7a039334031008386c5a8">SCB_CCSIDR_NUMSETS_Msk</a></div><div class="ttdeci">#define SCB_CCSIDR_NUMSETS_Msk</div><div class="ttdef"><b>Definition</b> core_armv81mml.h:885</div></div>
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<a id="ga3d672529cd193537fe2a0141931c6ad9" name="ga3d672529cd193537fe2a0141931c6ad9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3d672529cd193537fe2a0141931c6ad9">&#9670;&#160;</a></span>CCSIDR_WAYS</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CCSIDR_WAYS</td>
          <td>(</td>
          <td class="paramtype"></td>          <td class="paramname"><span class="paramname"><em>x</em></span></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(((x) &amp; <a class="code hl_define" href="group___c_m_s_i_s___c_o_r_e.html#gae093c4c635dad43845967512fa87173a">SCB_CCSIDR_ASSOCIATIVITY_Msk</a>) &gt;&gt; <a class="code hl_define" href="group___c_m_s_i_s___c_o_r_e.html#gae67f2f83976b819fb3039fc35cfef0fb">SCB_CCSIDR_ASSOCIATIVITY_Pos</a>)</div>
<div class="ttc" id="agroup___c_m_s_i_s___c_o_r_e_html_gae093c4c635dad43845967512fa87173a"><div class="ttname"><a href="group___c_m_s_i_s___c_o_r_e.html#gae093c4c635dad43845967512fa87173a">SCB_CCSIDR_ASSOCIATIVITY_Msk</a></div><div class="ttdeci">#define SCB_CCSIDR_ASSOCIATIVITY_Msk</div><div class="ttdef"><b>Definition</b> core_armv81mml.h:888</div></div>
<div class="ttc" id="agroup___c_m_s_i_s___c_o_r_e_html_gae67f2f83976b819fb3039fc35cfef0fb"><div class="ttname"><a href="group___c_m_s_i_s___c_o_r_e.html#gae67f2f83976b819fb3039fc35cfef0fb">SCB_CCSIDR_ASSOCIATIVITY_Pos</a></div><div class="ttdeci">#define SCB_CCSIDR_ASSOCIATIVITY_Pos</div><div class="ttdef"><b>Definition</b> core_armv81mml.h:887</div></div>
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<a name="doc-func-members" id="doc-func-members"></a><h2 id="header-doc-func-members" class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#gaf5585be5547cc60585d702a6129f4c17">&#9670;&#160;</a></span>SCB_CleanDCache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_CleanDCache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Clean D-Cache. </p>
<p>Cleans D-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gab86b0b49bac2b14b21cc1590009efac5">&#9670;&#160;</a></span>SCB_CleanDCache_by_Addr()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr </td>
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          <td class="paramtype">uint32_t *</td>          <td class="paramname"><span class="paramname"><em>addr</em></span>, </td>
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          <td class="paramtype">int32_t</td>          <td class="paramname"><span class="paramname"><em>dsize</em></span>&#160;)</td>
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<p>D-Cache Clean by address. </p>
<p>Cleans D-Cache for the given address D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes) </td></tr>
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  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5b22ca58709fadc326da83197a2f28bb">&#9670;&#160;</a></span>SCB_CleanInvalidateDCache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Clean &amp; Invalidate D-Cache. </p>
<p>Cleans and Invalidates D-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga853737b61ec075250d5991748fdd0e83">&#9670;&#160;</a></span>SCB_CleanInvalidateDCache_by_Addr()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr </td>
          <td>(</td>
          <td class="paramtype">uint32_t *</td>          <td class="paramname"><span class="paramname"><em>addr</em></span>, </td>
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          <td class="paramtype">int32_t</td>          <td class="paramname"><span class="paramname"><em>dsize</em></span>&#160;)</td>
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<p>D-Cache Clean and Invalidate by address. </p>
<p>Cleans and invalidates D_Cache for the given address D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes) </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gafe64b44d1a61483a947e44a77a9d3287">&#9670;&#160;</a></span>SCB_DisableDCache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_DisableDCache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Disable D-Cache. </p>
<p>Turns off D-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga56baa06298799dea5f207d4c12d9d4a6">&#9670;&#160;</a></span>SCB_DisableICache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_DisableICache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Disable I-Cache. </p>
<p>Turns off I-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga3861db932100ccb53f994e2cc68ed79c">&#9670;&#160;</a></span>SCB_EnableDCache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_EnableDCache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Enable D-Cache. </p>
<p>Turns on D-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga980ffe52af778f2535ccc52f25f9a7de">&#9670;&#160;</a></span>SCB_EnableICache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_EnableICache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Enable I-Cache. </p>
<p>Turns on I-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga99fe43c224644881935de135ceaa2dd9">&#9670;&#160;</a></span>SCB_InvalidateDCache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_InvalidateDCache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Invalidate D-Cache. </p>
<p>Invalidates D-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9945b206324ddbcd32818f1a4e49df83">&#9670;&#160;</a></span>SCB_InvalidateDCache_by_Addr()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr </td>
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          <td class="paramtype">void *</td>          <td class="paramname"><span class="paramname"><em>addr</em></span>, </td>
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          <td></td>
          <td class="paramtype">int32_t</td>          <td class="paramname"><span class="paramname"><em>dsize</em></span>&#160;)</td>
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<p>D-Cache Invalidate by address. </p>
<p>Invalidates D-Cache for the given address. D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are invalidated. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes) </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga62419cb7e6773e3d9236f14e458c1b05">&#9670;&#160;</a></span>SCB_InvalidateICache()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_InvalidateICache </td>
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          <td class="paramtype">void</td>          <td class="paramname"><span class="paramname"><em></em></span></td><td>)</td>
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<p>Invalidate I-Cache. </p>
<p>Invalidates I-Cache </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf6bed290ff6916337b0ce6c09131f699">&#9670;&#160;</a></span>SCB_InvalidateICache_by_Addr()</h2>

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          <td class="memname">__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr </td>
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          <td class="paramtype">void *</td>          <td class="paramname"><span class="paramname"><em>addr</em></span>, </td>
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          <td class="paramtype">int32_t</td>          <td class="paramname"><span class="paramname"><em>isize</em></span>&#160;)</td>
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<p>I-Cache Invalidate by address. </p>
<p>Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">isize</td><td>size of memory block (in number of bytes) </td></tr>
  </table>
  </dd>
</dl>

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